BASIC SYNTAX OF VERILOG

Verilog hdl is a structured programming language. Hardware is described in Verilog in terms of modules. Each Verilog programme consistes of atleast one module.
Module is the basic building block of every Vrilog hardware. Think of a module as an empty box with wires coming out and going in.These wires are termed as ports in the world of hardware description. Ports enable the module to communicate with the outside world, they provide an interface to the module for the outside environment. A simple module is shown below:



As you can see, there are three basic constituents of a module:

1. Input Ports: The connections to the module through which data and information can enter the module from the outside world.
2. Output Ports: The connections through which data or information can leave the module and go to the outside world.
3. Module Body: The main body or structure of the module itself. This is the part of the module which is responsible for all the activities and functionality of the module.

Keeping this bascic introduction of the module, the core of any Verilog description, we can look at a very basic Verilog program, a simple and gate example:

AND GATE IN VERILOG:
Consider a simple two input and gate description in Verilog. The general structure of and gate is described as:

1. Inputs: There are two inputs to and gate, a and b.
2. Outputs:There is single output named c.

The conventions for the names of inputs and outputs shall be discussed in greater detail later.

Verilog Code: Here is the module for and gate:

module and_gate(c , a, b);

output c;
input a ,b;

and (c , a , b);

endmodule