BASIC SYNTAX OF VERILOG

Verilog hdl is a structured programming language. Hardware is described in Verilog in terms of modules. Each Verilog programme consistes of atleast one module.
Module is the basic building block of every Vrilog hardware. Think of a module as an empty box with wires coming out and going in.These wires are termed as ports in the world of hardware description. Ports enable the module to communicate with the outside world, they provide an interface to the module for the outside environment. A simple module is shown below:



As you can see, there are three basic constituents of a module:

1. Input Ports: The connections to the module through which data and information can enter the module from the outside world.
2. Output Ports: The connections through which data or information can leave the module and go to the outside world.
3. Module Body: The main body or structure of the module itself. This is the part of the module which is responsible for all the activities and functionality of the module.

Keeping this bascic introduction of the module, the core of any Verilog description, we can look at a very basic Verilog program, a simple and gate example:

AND GATE IN VERILOG:
Consider a simple two input and gate description in Verilog. The general structure of and gate is described as:

1. Inputs: There are two inputs to and gate, a and b.
2. Outputs:There is single output named c.

The conventions for the names of inputs and outputs shall be discussed in greater detail later.

Verilog Code: Here is the module for and gate:

module and_gate(c , a, b);

output c;
input a ,b;

and (c , a , b);

endmodule

VERILOG INTORDUCTION

Verilog is a hardware description language (HDL) used to model electronic systems.
Verilog is most commonly used in the design, verification, and implementation of digital logic chips at the register transfer level (RTL) of abstraction. It is also used in the verification of analog and mixed-signal circuits. Verilog HDL has its roots in C language, as is clear by the overall structure of the language.Verilog is case-sensitive, has a basic preprocessor (though less sophisticated than that of ANSI C/C++), and equivalent control flow keywords (if/else, for, while, case, etc.), and compatible operator precedence. Syntactic differences include variable declaration (Verilog requires bit-widths on net/reg types, demarcation of procedural blocks (begin/end instead of curly braces {}), and many other minor differences.



History

Beginning:
Verilog was invented by Phil Moorby and Prabhu Goel during the winter of 1983/1984 at Automated Integrated Design Systems (renamed to Gateway Design Automation in 1985) as a hardware modeling language. Gateway Design Automation was purchased by Cadence Design Systems in 1990. Cadence now has full proprietary rights to Gateway's Verilog and the Verilog-XL simulator logic simulators. Originally, Verilog was intended to describe and allow simulation; only afterwards was support for synthesis added.

Verilog-95
With the increasing success of VHDL at the time, Cadence decided to make the language available for open standardization. Cadence transferred Verilog into the public domain under the Open Verilog International (OVI) (now known as Accellera) organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95. In the same time frame Cadence initiated the creation of Verilog-A to put standards support behind its analog simulator Spectre. Verilog-A was never intended to be a standalone language and is a subset of Verilog-AMS which encompassed Verilog-95.

Verilog 2001
Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that users had found in the original Verilog standard. These extensions became IEEE Standard 1364-2001 known as Verilog-2001. Verilog-2001 is a significant upgrade from Verilog-95. First, it adds explicit support for (2's complement) signed nets and variables. Previously, code authors had to perform signed-operations using awkward bit-level manipulations (for example, the carry-out bit of a simple 8-bit addition required an explicit description of the boolean-algebra to determine its correct value). The same function under Verilog-2001 can be more succinctly described by one of the built-in operators: +, -, /, *, >>>. A generate/endgenerate construct (similar to VHDL's generate/endgenerate) allows Verilog-2001 to control instance and statement instantiation through normal decision-operators (case/if/else). Using generate/endgenerate, Verilog-2001 can instantiate an array of instances, with control over the connectivity of the individual instances. File I/O has been improved by several new system-tasks. And finally, a few syntax additions were introduced to improve code-readability (e.g. always @*, named-parameter override, C-style function/task/module header declaration). Verilog-2001 is the dominant flavor of Verilog supported by the majority of commercial EDA software packages. Verilog 2005 Not to be confused with SystemVerilog, Verilog 2005 (IEEE Standard 1364-2005) consists of minor corrections, spec clarifications, and a few new language features (such as the uwire keyword). A separate part of the Verilog standard, Verilog-AMS, attempts to integrate analog and mixed signal modeling with traditional Verilog.